1. Technical Field
The present application relates to a technology for controlling the order of responses to be transmitted from a plurality of slaves to a bus master in response to requests transmitted from the bus master to the plurality of slaves in a semiconductor integrated circuit including a network of semiconductor buses.
2. Description of the Related Art
For efficient development of integrated circuits made in order to realize an intended function or performance, it is attempted to reuse and connect existing bus masters. In this type of development, it is required that various types of bus masters that are different in the bus width, the bus protocol and the required quality should be easily connectable to each other.
Such various types of bus masters are different in the number of slaves to be accessed, the number of bus interfaces, and the size of the receiving buffer. Therefore, for connecting various types of bus masters, bus interfaces need to be designed so as to provide transmission performance required of each bus master.
Japanese Patent No. 3086261 discloses a technology for improving the transmission performance between a bus master and a plurality of slaves. The technology in Japanese Patent No. 3086261 physically increases the number of bus interfaces of the bus master, so that a logical bus including a plurality of physical buses can be used to expand the transmission band of access to a memory.